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episode 31: one year anniversary, RC2018/09 results, FPGA and Forth
Yay, after one year we're still polluting the virtual airwaves, so let's review the last year of podcasting (only takes about 8 minutes - don't cry). RetroChallenge RC2018/09 has finished, so we take a look at its winners and honourable mentions. Minor topics include a Hackalot visit, USB nullmodem hack, breadboard fail and fried scope probe clip. I briefly tried to generate a VGA image from software, but why not do it using an FPGA next time? Following convo deals with my initial experience with the Lattice ICEstick (iCE40HX1K) FPGA devboard, supported by a completely open toolchain (Yosys, Arachne-PNR, IceStorm). The J1(a) CPU is a small Forth-aimed CPU in Verilog, which leads yours truly into the weird and wonderful world of the Forth programming language. RetroChallenge 2018/09 contestants and final results Hackalot hackspace (.nl, text in Dutch) iCE40 FPGA: Lattice iCEstick USB FPGA devboard (iCE40HX1K) Yosys RTL synthesis tool for Xilinx 7 and Lattice iCE40 Arachne-PNR place & route tool for Lattice iCE40 IceStorm bitstream manipulation tools for Lattice iCE40 iCE40 FPGA & Forth: Swapforth for the J1a CPU and other platforms Swapforth explicitly for the J1a CPU Swapforth reference targeted at iCEstick, including memory map and peripheral access Forth: Gforth manual (HTML) or in PDF format - EXCELLENT Thinking Forth book by Leo Brodie Starting Forth by Leo Brodie (PDF), or in HTML format Programming Forth by Stephen Pelc HCC Retro division (in Dutch) - seems a bit outdated perhaps Nullmodem hack using homebrew module: Lame VGA image: Fancy VGA adapter:  
CBA Podcast
http://podcast.cba.si
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